a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture, and more particularly to a semiconductor device with memories of high integration and its manufacture.
b) Description of the Related Art
Still higher integration is required for semiconductor integrated circuit devices. Requirements of high integration are particularly strong in dynamic random access memory (DRAM) devices.
One memory cell of DRAM is generally constituted of one memory capacitor and one transistor. A transistor used is generally an insulated gate (IG) field effective transistor (FET) having a pair of source/drain regions, a channel coupling the source/drain regions, and an insulated gate electrode disposed above the channel for controlling the conductivity of the channel The IG FET is typically a metal-oxide-semiconductor (MOS) FET.
A memory capacitor is connected to one (hereinafter called a source, as a matter of convenience) of source/drain regions, and a bit line is connected to the other hereinafter called a drain as a matter of convenience). A word line is connected to the insulated gate electrode. In order to realize high integration, it is desired to make memory cells of a fine pattern and dispose a plurality of bit lines and word lines at a narrow pitch. Various techniques have been proposed to dispose bit and word lines at a high density.
It is also desired that DRAM has excellent retention (storage) characteristics which show how long electric charges in the capacitor can be retained.